PMOS
ON
Gate LOW → |VGS| > |Vtp| → conducts. VDD → output.
NMOS
OFF
Gate LOW → VGS < Vtn → cut off. No path to GND.
Output
HIGH (1)
Pulled to VDD through conducting PMOS.
Truth Table
IN
PMOS
NMOS
OUT
0
ON
OFF
1
1
OFF
ON
0
PMOS P1 (input A)
ON
A is LOW → P1 conducts.
PMOS P2 (input B)
ON
B is LOW → P2 conducts.
NMOS N1 (input A)
OFF
A is LOW → N1 cut off. Series path broken.
NMOS N2 (input B)
OFF
B is LOW → N2 cut off. Series path broken.
Output
HIGH (1)
Either PMOS conducts → output pulled to VDD.
Truth Table
A
B
PMOS
NMOS
OUT
0
0
Both ON
Both OFF
1
0
1
P1 ON
N1 OFF
1
1
0
P2 ON
N2 OFF
1
1
1
Both OFF
Both ON
0
PMOS P1 (input A)
ON
A is LOW → P1 conducts.
PMOS P2 (input B)
ON
B is LOW → P2 conducts.
NMOS N1 (input A)
OFF
A is LOW → N1 cut off.
NMOS N2 (input B)
OFF
B is LOW → N2 cut off.
Output
HIGH (1)
Both PMOS in series conduct → output pulled to VDD.
Truth Table
A
B
PMOS
NMOS
OUT
0
0
Both ON
Both OFF
1
0
1
P2 OFF
N2 ON
0
1
0
P1 OFF
N1 ON
0
1
1
Both OFF
Both ON
0