NAND D Latch
Gate-level interactive implementation using 4 NAND gates
D = 0
0
EN = 0
0
LATCHED (Holding)
S'R" Latch Topology
INV
&
NAND1
&
NAND2
&
NAND3
&
NAND4
D
EN
S_bar
R_bar
Q
Q_bar
Live Timing
Logic Log