FIFO Buffer

First-In, First-Out queue bridging clock domains

⚡
Fast Producer
100 MHz
CLK
→
WRITE
FIFO Buffer
0 / 8
WR_PTR: 0
RD_PTR: 0
Empty Full
→
READ
🐢
Slow Consumer
10 MHz
CLK
EMPTY
ALMOST EMPTY
ALMOST FULL
FULL
0
Written
0
Read
0
Overflow
0
Underflow
Write Speed:
Read Speed:

📚 What is a FIFO?

A FIFO (First-In, First-Out) buffer is a queue data structure commonly used in digital systems to transfer data between components operating at different speeds or clock domains. Data written first is read first, maintaining order.

⚡ Why Use a FIFO?

  • Clock domain crossing - safely pass data between different clock frequencies
  • Rate matching - buffer bursts from fast producers for slower consumers
  • Data buffering - smooth out irregular data arrival patterns

🚩 Status Flags

  • EMPTY - no data available to read
  • FULL - no space available to write
  • ALMOST EMPTY/FULL - early warning thresholds

⚠️ Common Issues

  • Overflow - writing when full loses data
  • Underflow - reading when empty returns invalid data
  • Metastability - must synchronize pointers across clock domains