Initial Block Signals with Parametric Delays

Adjust delays and clock half-period; see the resulting signal timeline.
Verilog (auto-filled from your inputs)

            

                
                
            

            
            
Enter simple #delay signal = value; lines inside the initial block. Each
                delay is relative to the previous statement (just like Verilog). Signals: vec (4-bit),
                sigA, sigB. Clock is driven separately by the half-period above.

        


        

            
Timing diagram (step waveform)

            

                
            

            
Clock toggles every half-period; other signals update at their scheduled #delays. The
                diagram shows step waveforms over time.