RTL Schematic
Click switches to toggle inputs
Status: Waiting...
Verilog Source
module mux_2to1_1bit (
input wire i0,
input wire i1,
input wire sel,
output wire y
);
// Continuous Assignment
// If sel is 1, y = i1
// If sel is 0, y = i0
assign y = sel ? i1 : i0;
endmodule
Logic Analysis
Current state explanation...