RTL Schematic
Click inputs to cycle values (Hex)
Status: Waiting...
Verilog Source
module mux_2to1_4bit (
input wire [3:0] i0,
input wire [3:0] i1,
input wire sel,
output wire [3:0] y
);
// Continuous Assignment (Bus Width 4)
// If sel is 1, y = i1 (4 bits)
// If sel is 0, y = i0 (4 bits)
assign y = sel ? i1 : i0;
endmodule
Logic Analysis
Current state explanation...