RTL Schematic
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0-3
Status: Waiting...
Verilog Source
module mux_4to1_4bit (
input wire [3:0] i0, i1, i2, i3,
input wire [1:0] sel,
output reg [3:0] y
);
always @(*) begin
case (sel)
2'd0: y = i0;
2'd1: y = i1;
2'd2: y = i2;
2'd3: y = i3;
endcase
end
endmodule
Logic Analysis
Current state explanation...