RTL Design vs Testbench

Understanding the separation between synthesizable hardware and simulation-only code

🧪 Testbench Simulation-only code that tests your design. Generates input signals, instantiates your module, and checks outputs. Never synthesized!

→ Simulation Only

📄 Design Module (RTL) Describes actual hardware that gets synthesized onto the FPGA. Defines inputs, outputs, and the logic between them.

→ Goes on FPGA

🧪 Testbench Simulation Only

tb_counter.v — Drives inputs, checks outputs

                    // Testbench - NOT synthesizable!
                    module tb_counter;
                    
                    // Testbench signals (directly drives design inputs)
                      reg clk;           // TB generates clock
                      reg reset;         // TB controls reset
                      reg enable;        // TB controls enable
                    
                    // Wires to observe design outputs
                      wire [3:0] count;  // Observe counter value
                      wire overflow;      // Observe overflow flag
                    
                    // Instantiate the Design Under Test (DUT)
                      counter DUT (
                        .clk(clk),
                        .reset(reset),
                        .enable(enable),
                        .count(count),
                        .overflow(overflow)
                      );
                    
                    // Generate clock (simulation only!)
                      always #5 clk = ~clk;
                    
                    // Test sequence
                      initial begin
                        clk = 0;
                        reset = 1;
                        enable = 0;
                        #20 reset = 0;
                        #10 enable = 1;
                        #200 $finish;
                      end
                    
                    endmodule
                

📄 Design Module Synthesizable RTL

counter.v — Actual hardware description

                    // Synthesizable RTL - becomes real hardware!
                    module counter (
                      input  wire clk,         // Clock input
                      input  wire reset,       // Reset input
                      input  wire enable,      // Enable input
                      output reg  [3:0] count, // 4-bit count
                      output wire overflow     // Overflow flag
                    );
                    
                      // Overflow when count reaches max
                      assign overflow = (count == 4'hF);
                    
                      // Counter logic
                      always @(posedge clk) begin
                        if (reset)
                          count <= 4'b0;
                        else if (enable)
                          count <= count + 1;
                      end
                    
                    endmodule
                

Module Port Diagram

clk →

reset →

enable →

→

counter

Design Module

→

→ count[3:0]

→ overflow

🧪 RTL Design vs Testbench