Circuit Schematic
A B NOT A' NOT B' AND A'B AND AB' OR F
Input A: 0
Input B: 0
Timing Diagram
A
B
A'
B'
A'B
AB'
F
Inputs (A, B)
Intermediate Signals
Output (F)
1
NOT: 300ms delay
2
AND: 300ms delay
3
OR: 300ms delay