Verilog Simulation: Time Ticks & Scheduled Updates

Each tick: processes read the current signals, schedule assignments, then values change together at the end of the tick.
Tick 0 | clk=0 req=0 ack=0 | pending: none
Time axis (latest tick glows)
Process being simulated
always @(posedge clk) begin
  ack <= req;          // sample request on the rising edge
end
Current signals
Processes see the values that exist at the start of the tick. Any assignments they make land together at the end of that same tick.
Reading this diagram
1 / asserted
0 / deasserted
Use Next tick or Play to move time forward. You can queue an external change to req before the next tick. The simulator will: read signals → run the process → apply scheduled updates.