Verilog Vectors
Concatenation
{}
, Replication
{N{}}
, and Part Select
[:]
Normal {a,b,c,d}
Reverse {d,c,b,a}
Replicate {4{a}}
Split [Hi:Lo]
d
c
b
a
assign bus = {a, b, c, d};
4
4'b0000
wire [3:0] bus;
bus[3]
bus[2]
bus[1]
bus[0]
assign out = bus;
out[3]
out[2]
out[1]
out[0]